Monolithic ICs generally comprise a number of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated over a planar substrate, such as a silicon wafer.
ICs often include at least one fuse. A fuse is a sacrificial device to provide overcurrent protection, security, or programmability. A fuse starts with a low electrical resistance and is designed to permanently create a non-conductive path when the current across the device exceeds a certain level.
Some conventional fuse designs employ a thin interconnect metal line. If a high enough current is passed through the thin metal line, the line melts and creates an open circuit. To have a low program current, the cross-section of the fuse needs to be small compared to other circuit conductors. Another fuse design leverages electromigration between two metal materials. When two or more conducting metals interface, momentum transfer between conduction electrons and metal ions can be made large where there is a non-uniform metal ion lattice structure. Above a certain current level, atoms move and create voids near the bimetal interface, thus creating open circuit. In such a fuse design, the overlap area between metals and the electromigration properties of the metals determine the fuse program current.
With MOS transistor dimensions scaling from one technology generation to the next, it is also desirable to scale down fuse size, as well as fuse program current. However, fuse architectures typically rely on less critical lithographic patterning capability than is employed for the smallest MOS transistor structures, and so have not been on the same scaling trajectory as the MOS transistor. Fuse architectures dependent on a bimetal overlap area are typically also limited by lithographic patterning (e.g., overlay) capability. Furthermore, fuse architectures reliant on electromigration are generally incompatible with efforts to mitigate electromigration for sake of improve device reliability.
Fuse architectures and associated fabrication techniques capable of lower program currents, and/or smaller fuse areas are therefore advantageous for advanced MOS ICs.